1. Field of Invention
This invention relates generally to semiconductor memories and specifically to a method of addressing multiple locations of a memory device.
2. Description of Related Art
In some applications such as, for instance, video graphics, it is desirable to write the same data, e.g., pixel information, to a plurality of bits of an associated memory device. In such applications, data is typically written simultaneously to memory cells within more than one column of the memory device. As explained below, the simultaneous writing of data to memory cells within multiple columns of a memory device typically requires a large driver circuit.
FIG. 1 shows a portion 10 of a conventional DRAM array having two columns C0 and C1, where each column C includes two associated memory cells 12. Each memory cell 12 includes a pass transistor T and a storage capacitor C. For instance, memory cell 12a, which lies in the first row of column C0, includes a pass transistor Ta and a storage capacitor Ca. The binary state of a cell 12 is determined in a well known manner by sensing the differential voltage across the complementary bit lines BL and BL associated with that cell 12. For instance, to read cell 12a, an appropriate read voltage is applied to word line WL0 and to isolation node ISO, thereby turning on pass transistor Ta and isolation transistors 14, respectively. The un-selected word lines (e.g., WL1) are held at a low voltage such as, for instance, ground potential, so that the pass transistors Tb and Tc of memory cells 12b and 12c, respectively, are non-conductive. If the storage capacitor Ca of memory cell 12a is charged, thereby indicating that memory cell 12a is in a programmed state, i.e., representing a binary "1", latch 16a assumes a first binary state in which the voltage on bit line BL0 is higher than the voltage on the bit line BL0. If, on the other hand, the storage capacitor Ca is not charged, thereby indicating that memory cell 12a is in an erased state, i.e., representing a binary "0", latch 16a assumes a second binary state in which the voltage on bit line BL0 is higher than the voltage on bit line BL0. A column address strobe (CAS) signal (not shown for simplicity) is pulsed on the column node C0 to allow the differential voltage across complementary bit lines BL0 and BL0 to appear across lines complementary lines WD and WD via pass transistors 18a. This differential voltage is provided to the sense amplifier 20 which, in response thereto, ascertains the binary data stored in the cell 12a.
When writing to one of the memory cells 12, externally generated data is provided to a conventional input logic circuit 21 which, in response thereto, provides appropriate signals to the write data drivers 22. For instance, to write a binary "1" to cell 12a, the word line WL0, isolation node ISO, and column node C0 are driven to a high voltage so as to turn on transistors Ta, 14, and 18a, respectively. Driver 22a drives the write data line WD to a voltage greater than the threshold voltage V.sub.T of the latch 16a, while driver 22b pulls the complementary write data line WD to a voltage lower than the V.sub.T of the latch 16a. As a result, the latch 16a transitions to the first binary state where, as discussed earlier, the bit line BL0 is at a higher voltage than is the complementary bit line BL0. The higher voltage on the bit line BL0 charges the capacitor Ca of cell 12a, thereby writing a "1" to the cell 12a.
Conversely, a binary "0" is written to cell 12a by pulling the bit line BL0 to a low voltage (below the V.sub.T of the latch 16a) while driving the complementary bit line BL0 to a high voltage (above the V.sub.T of the latch 16a). Here, the latch 16a is driven to the second binary state to ensure that charge does not accumulate on the capacitor Ca of cell 12a.
Due to the inherent resistance of the write data lines WD and WD, the attenuation of signals provided by the drivers 22a and 22b increases as the signals propagate along on the lines WD and WD, respectively. Thus, signal attenuation is greater when writing data to memory cells further away from the write drivers 22, i.e., signal attenuation is greater when writing data to memory cell 12d than when writing data to memory cell 12a. Accordingly, increasing the number of columns in a memory array requires a corresponding increase in the size of the associated drivers 22.
When simultaneously writing data to the memory cells 12 of more than one column, a much larger signal current is required which, in turn, requires a corresponding increase in the drive capability and thus size of the drivers 22. FIG. 2 shows a DRAM array 30 having 256 columns C of the type shown in FIG. 1, where each of the columns of the array 30 contains N of the memory cells 12. Data is written to and read from the cells 12 of the array 30 in a conventional manner, as described above with respect to the array portion 10 shown in FIG. 1. Each of the columns C is coupled to an associated column node N0-N255 and is assigned a column address 0-255, as shown in FIG. 2. The write data line WD is driven by a conventional write driver 34 in response to data received by an input logic circuit 32. The complementary write data line WD and its associated driver are not shown in FIG. 2 for simplicity.
To simultaneously write data to the memory cells within more than one of the columns C of the array 30, the columns containing the memory cells desired to be written to are first selected in a conventional manner by an associated decode circuit (not shown for simplicity). Once the desired columns are selected for writing, externally generated data is provided in a well known manner to the logic circuit 32 which, in turn, provides appropriate control signals to the write driver 34 in a well known manner. In response thereto, the write driver 34 drives the latches 16 (not shown in FIG. 2) within each of the selected columns to either the first or second binary state, as determined by the data received via the logic circuit 32. To properly program the selected cells, the write driver 34 must drive each of those nodes NO-255 associated with the selected columns to a voltage which exceeds the threshold V.sub.T of the latches therein.
As mentioned earlier, the signals generated by the driver 34 attenuate as they propagate along the write data line WD. The voltage drop V.sub.n along line WD between the write driver 34 and the column at node Nn may be expressed as V.sub.n =IR.sub.n, where n is an integer between 0 and 255 inclusive, I is the current necessary to drive one of the latches 16, and R.sub.n is the resistance of the write data line WD between the output terminal of driver 34 and node Nn. For instance, assuming the resistance of the write data line WD between adjacent columns is equal, and may thus be expressed as R.sub.c, the resistance of the write data line WD between the driver 34 and the column at node NO is equal to R.sub.c, the resistance of the write data line WD between the driver 34 and the column at node N1 is equal to 2R.sub.c, and so on, such that the resistance of the write data line WD between the driver 34 and the column at node N255 is equal to 256R.sub.c.
For instance, where it is desired to simultaneously write data to the memory cells in eight consecutively addressed columns, the write driver 34 should provide a signal current of 8I onto the write data line WD. The attenuation of this signal is equal to approximately 8IR.sub.ave, where R.sub.ave is the average resistance of the write data line WD between the driver 34 and each of the selected columns. Thus, the signal attenuation associated with simultaneously writing data to the memory cells within the eight consecutively addressed columns closest to the write driver 34, i.e., the columns corresponding to the column nodes N0-N7, is given by: ##EQU1##
The signal attenuation associated with simultaneously writing data to the memory cells 12 within the eight consecutively addressed column furthest from the write driver 34, i.e., the columns corresponding to the column nodes N248-N255, is given by: ##EQU2##
Accordingly, since the maximum signal attenuation associated with simultaneously writing data to the memory cells within eight columns of the array 30 is equal to approximately 2020IR.sub.c, the write driver 34 must provide sufficient signal current on the write data line WD to compensate for an attenuation loss of approximately 2020IR.sub.c. Otherwise, the attenuation of signals generated by the write driver 34 and provided on the write data line WD may not be sufficient to properly program the memory cells within one or more of the selected columns. It is therefore desirable to reduce the maximum signal attenuation required when simultaneously writing data to memory cells within multiple columns so that the drive-capability and thus the size of the write driver 34 may be reduced.